The present invention relates in general to integrated circuits, and in particular to a slew rate limited output driver circuit that minimizes switching current while delivering sufficient peak load current.
Integrated circuits developed for applications such as data or telecommunication systems are often required to comply with certain standardized interface specifications. For example, to comply with the RS232 interface standard, an output driver circuit must be capable of driving a resistive load of about 3-7K Ohms with a voltage swing of greater than .+-.5 volts. The RS232 driver circuit must also be capable of driving a capacitive load of about 2500 pF at a frequency of about 20 KHz. Another requirement is a minimum of 300 Ohms of output impedance for the driver circuit under power off conditions.
In addition to the above requirements, the RS232 driver circuit must exhibit a slew rate no more than 30 volts/.mu.sec to minimize undesirable high frequency components of the output signal that cause radiation. To meet all of these requirements places severe constraints on the design of the output driver. A conventional output driver is typically made of a CMOS inverter with a p-channel pull-up transistor and an n-channel pull-down transistor. The n-channel and p-channel transistors in the CMOS inverter are often over-designed in order to be able to supply enough current to a 3K Ohm resistive load while the output swings all the way from -5 volts to +5 volts at a maximum rate of 30 volts/.mu.sec. The over-designing of the CMOS inverter results in large amounts of switching (or crow-bar) current.
There is therefore a need for an improved slew-rate limited output driver circuit that is capable of supplying the required peak load current while minimizing switching current.